Following is a plain text list of my selected publications followed by abstracts. Each item had a bibtex reference for your convenience: Journals: ==================================================================================================== S.S. Akbay, A. Halder, A. Chatterjee, D. Keezer, "Low Cost Test of Embedded RF/Analog/Mixed-Signal Circuits in SOPs," IEEE Trans. on Advanced Packaging, vol. 27, iss. 2, pp. 352-363, May 2004. Abstract: Increasing levels of integration and high speeds of operation have made the problem of testing complex systems-on-packages very difficult. Testing packages with multi-gigahertz RF and optical components is even more difficult as external tester costs tend to escalate rapidly beyond 3 GHz. The extent of the problem can be gauged by the fact that test cost is approaching almost 40% of the total manufacturing cost of these packages. To alleviate test costs, various solutions relying on built-off test (BOT) and built-in test (BIT) of embedded high-speed components of SOPs have been developed. These migrate some of the external tester functions to the tester load board (BOT) and to the package and the die encapsulated in the package (BIT) in an 'intelligent' manner. This paper provides a discussion of the emerging BOT and BIT schemes for embedded high-speed RF/analog/mixed-signal circuits in SOPs. The pros and cons of each scheme are discussed and preliminary available data on case studies are presented. @ARTICLE{akbaySOP, Author = {S.S. Akbay and A. Halder and A. Chatterjee and D. Keezer}, Journal = {IEEE Trans. on Advanced Packaging}, Month = {May}, Number = {2}, Pages = {352-363}, Title = {Low Cost Test of Embedded {RF}/Analog/Mixed-Signal Circuits in {SOP}s}, Volume = {27}, Year = {2004}, Language = {English} } -------------------------------------------------------------------------------------------------------- R. Voorakaranam, S. Cherubal, S.S. Akbay, A. Chatterjee, "Signature Testing of Analog and RF Circuits: Algorithms and Methodology," submitted to IEEE Transactions on Circuits and Systems. Abstract: Production test costs for today's RF and high-speed analog circuits are rapidly escalating. Two factors are responsible for this cost escalation: (a) the high cost of high-speed ATEs and (b) long test times required by elaborate performance tests. In this paper, we propose a low-cost signature test methodology for accelerated production testing of analog and RF circuits. As opposed to prior work, the proposed algorithm directly tracks the ability to predict the test specification values from the observed test response in the presence of measurement noise. The test methodology is applied to low cost signature test of RF circuits using modulation of a baseband test stimulus and demodulation of the obtained response. The demodulated response of the DUT is used as a 'signature' from which all the performance specifications are predicted. The applied test signal is optimized in such a way that the error between the measured DUT performances and the predicted DUT performances is minimized. The proposed low-cost solution can be easily built into a load board that can be interfaced to an inexpensive tester. @ARTICLE{voorCAS1, Author = {R. Voorakaranam and S. Cherubal and S.S. Akbay and A. Chatterjee}, Journal = {IEEE Transactions on Circuits and Systems}, Note = {In Progress}, Title = {Signature Testing of Analog and {RF} Circuits: Algorithms and Methodology}, Language = {English} } ------------------------------------------------------------------------------------------------------- Conference Proceedings: ==================================================================================================== S.S. Akbay, J. L. Torres, J. M. Rumer, A. Chatterjee, J. Amtsfield, "Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation," Proc. International Test Conference, Santa Clara, CA, USA, Oct. 2006. Abstract: This paper summarizes an alternate test methodology that enables significant reduction in testing time and tester complexity for RF circuits without the need for low level simulation models. Traditionally, alternate test makes use of circuit and process level models to analyze the sensitivity of datasheet specifications to the variations in process parameters. In this paper, we demonstrate a 'gray-box' approach by creating a high level simulation model from datasheet information and simple hardware measurements. This model is used together with a customized behavioral simulator to enable efficient search of an alternate test stimulus that is optimal in terms of tester constraints, test time and specification prediction accuracy. The specific example is a third party RF front end chip, for which 13 specifications including S parameters, intermodulation products and noise figures are measured with both conventional and alternate methods. The results are compared in terms of testing time, tester cost and accuracy. @INPROCEEDINGS{akbayITC06, Address = {Santa Clara, CA, USA}, Author = {S. S. Akbay and J. L. Torres and J. M. Rumer and A. Chatterjee and J. Amtsfield}, Booktitle = {Proc. IEEE International Test Conference}, Pages = {243-248}, Month = {October}, Title = {Alternate Test of {RF} Front Ends with {IP} Constraints: Frequency Domain Test Generation and Validation}, Year = {2006}, Language = {English} } ------------------------------------------------------------------------------------------------------- S.S. Akbay, A. Chatterjee, "Built-In Test of RF Components Using Mapped Feature Extraction Sensors," Proc. 23rd IEEE VLSI Test Symposium, Palm Springs, CA, USA, May 2005. Abstract: At low frequencies, alternate testing is based on sampling the test response using an A/D converter and analyzing the digitized response in the external tester. In order to use alternate test at frequencies in the multi-GHz range, where the above is not possible, the test waveforms need to be very simple and the evaluation of the test response needs to be handled by on chip analog test response 'feature extractors'. In this work, specialized functions of the output response from an alternate test are computed using built-in feature extraction sensors, which measure a complex function of the response waveform and output a DC signature. Different sensor structures are evaluated based on their performance in the presence of environmental effects and process shifts It is seen that very simple sensing circuitry can predict high quality alternate test for RF components. @INPROCEEDINGS{akbayVTS05, Address = {Palm Springs, CA, USA}, Author = {S.S. Akbay and A. Chatterjee}, Booktitle = {Proc. 23rd IEEE VLSI Test Symposium}, Pages = {243-248}, Month = {May}, Title = {Built-In Test of {RF} Components Using Feature Extraction Sensors}, Year = {2005}, Language = {English} } ------------------------------------------------------------------------------------------------------- S.S. Akbay, A. Chatterjee, "Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference," Proc. 22nd IEEE VLSI Test Symposium, Napa Valley, CA, USA, April 2004, pp. 273-278. Abstract: This paper addresses the cost, signal integrity and I/O bandwidth problems in radio-frequency testing by proposing a feature extraction based built-in alternate test scheme. The scheme is suitable for built-in self-test of radio-frequency components embedded in a system with available digital signal processing resources, and can also be extended to implement built-in test solutions for individual RF devices that have access to a low-end digital tester. The process applies an alternate test and automatically extracts features from the component response to predict specifications like third order intercept point, 1dB compression point, noise figure, gain and power supply rejection ratio. The proposed scheme makes use of low-speed lowresolution undersampling to eliminate the need for a bulky analog-to-digital converter and the use of a noise reference for comparison makes it possible to compensate for imperfect stimulus generation. The simulation results for a 1 GHz downconversion mixer and a 900 MHz low-noise amplifier present an average of 97.3% prediction accuracy of specifications under test. @INPROCEEDINGS{akbayVTS04, Address = {Napa Valley, CA, USA}, Author = {S.S. Akbay and A. Chatterjee}, Booktitle = {Proc. 22rd IEEE VLSI Test Symposium}, Month = {April}, Pages = {273-278}, Title = {Feature Extraction Based Built-In Alternate Test of {RF} Components Using a Noise Reference}, Year = {2004}, Language = {English} } ------------------------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------------------------- D. Han, S.S. Akbay, S. Bhattacharya, A. Chatterjee, W.R. Eisenstadt, "On-Chip Self Calibration of RF Circuits Using Specification-Driven Built-In Self Test," Proc. 11th IEEE International Online Testing Symposium, July 2005, pp. 106-111. Abstract: In the nanometer design regime, analog and RF circuits are expected to be increasingly susceptible to process, noise and thermal variations. Shifting threshold voltages on the NMOS and PMOS devices of a mixer, LNA or power amplifier, for example, can affect the design specifications of such circuits (such as gain) . Thermal variations can affect carrier mobilities of NMOS and PMOS devices differently, further affecting circuit perform ance. To solve these problems, a new self-calibration approach driven by a Specification- driven Built-In Self-Test procedure (S-BIST) is proposed. This S-BIST procedure uses alternate specification test techniques to predict the performance specifications of the circuit-under-test from the S-BIST response. The results of the S-BIST procedure are used to change the operating point of the circuit to maximally compensate the analog/RF circuit for loss of performance. The proposed S-BIST approach has been applied to a 2.4 GHz low noise amplifier and performs well in the presence of temperature and process variations. @INPROCEEDINGS{hanIOLTS05, Author = {D. Han and S.S. Akbay and S. Bhattacharya and A. Chatterjee and W.R. Eisenstadt}, Booktitle = {Proc. 11th IEEE International Online Testing Symposium}, Month = {July}, Pages = {106-111}, Title = {On-Chip Self Calibration of {RF} Circuits Using Specification-Driven Built-In Self Test}, Year = {2005}, Language = {English} } ------------------------------------------------------------------------------------------------------- Workshop Papers: ==================================================================================================== S.S. Akbay, A. Chatterjee, "Comprehensive Catastrophic and Parametric Fault Testing Using the Alternate Test Approach," Proc. IEEE Int. Workshop on Current & Defect Based Testing (DBT), Santa Clara, CA, USA, October 2006. Abstract: Alternate test methodology provides significant test time and equipment cost reduction for test of analog and radio frequency devices by crafting a single test stimulus and mapping the response signatures into all specifications at once. Although many previous publications reported successful implementations of alternate test, their focus has been parametric faults resulting from variations in process parameters; they do not include a systematic method to guarantee that all catastrophic faults are detected as well. In this paper, we propose a signature filtering mechanism which can be used with regular alternate test flow in order to effectively mark out catastrophic faults. The scheme makes use of a training set of parametric faults only, hence does not assume any predefined fault list. The case study on a lownoise amplifier shows that the proposed scheme can differentiate catastrophic defects with 100% coverage. @INPROCEEDINGS{akbayDBT06, Address = {Santa Clara, CA, USA}, Author = {S.S. Akbay and A. Chatterjee}, Booktitle = {Proc. IEEE Int. Workshop on Current & Defect Based Testing (DBT)}, Month = {October}, Title = {Comprehensive Catastrophic and Parametric Fault Testing Using the Alternate Test Approach}, Year = {2006}, Language = {English} } ------------------------------------------------------------------------------------------------------- S.S. Akbay, A. Chatterjee, "Temperature Compensated Built-In Alternate Test of RF Modules," Digest of 1st IEEE International GHz/Gbps Test Workshop, Charlotte, NC, USA, October 2004. Abstract: At low frequencies, alternate testing of analog modules is based on sampling the test response using an A/D converter and analyzing the digitized response in the external tester. In order to use alternate test at frequencies in the multi-GHz range with RF components, both the test waveforms need to be very simple and the evaluation of the test response should be handled by practical hardware-based test response feature-extractors. One such scheme employs sensors that measure a complex function of the response waveform and output a DC signature which can easily be collected by a low-cost external tester or can be evaluated by system resources available on chip/package. In this work, we demonstrate the first temperature compensated alternate test, which makes use of built-in feature extraction sensors. The simulation study on a 900 MHz low-noise amplifier (LNA) shows accurate prediction of IIP3, 1dB compression point and noise figure specifications even when the operation temperature of the LNA is not monitored by external means throughout the testing process. @INPROCEEDINGS{akbayGTW04, Address = {Charlotte, NC, USA}, Author = {S.S. Akbay and A. Chatterjee}, Booktitle = {Digest of 1st IEEE International GHz/Gbps Test Workshop}, Month = {October}, Title = {Temperature Compensated Built-In Alternate Test of {RF} Modules}, Year = {2004}, Language = {English} } ------------------------------------------------------------------------------------------------------- S.S. Akbay, A. Chatterjee, "Alternate Test of RF Mixers by Current Signatures," Digest of 3rd Workshop on Test of Wireless Circuits and Systems, International Microwave Symposium, Fort Worth, TX, USA, June 2004. Abstract: This paper describes an alternate test methodology for radio-frequency mixers. The methodology is based on current signatures obtained by sampling the filtered supply current when the circuit-under-test is stimulated by a single tone sinusoidal. Sampling of supply current instead of voltage eliminates the parasitics and loading due to test circuitry on the signal path, hence provides a non-invasive built-in-self-test methodology. Furthermore, the experiments show that specification prediction accuracy is not significantly degraded by decreasing the stimulus power. The goal of the paper is to examine the advantages and disadvantages of current-based alternate tests and provide feasibility analysis for future directions. @INPROCEEDINGS{akbayWTW04, Address = {Fort Worth, TX, USA}, Author = {S.S. Akbay and A. Chatterjee}, Booktitle = {Digest of 3rd Workshop on Test of Wireless Circuits and Systems, International Microwave Symposium}, Month = {June}, Title = {Alternate Test of {RF} Mixers by Current Signatures}, Year = {2004}, Language = {English} } ------------------------------------------------------------------------------------------------------- S.S. Akbay, A. Chatterjee, "Optimal Multisine Tests for RF Amplifiers," Digest of 2nd IEEE Workshop on Test of Wireless Circuits and Systems, Baltimore, MD, USA, October 2002. Abstract: With trends towards higher speed circuits, the cost of testing is beginning to dominate the overall manufacturing cost of high-speed components. To solve this problem, test complexity must be reduced dramatically. Prior research indicates that complex specification tests can be replaced by simpler tests from which many specification values can be extracted concurrently. In this paper, an optimal multisine test generation approach for RF amplifiers is presented. The goal of the paper is to examine tradeoffs between test complexity and process-variation induced failure coverage. It is shown that some complex specifications can be tested accurately using test signal frequencies significantly below the operating frequency of the RF circuit-under-test. @INPROCEEDINGS{akbayWTW02, Address = {Baltimore, MD, USA}, Author = {S.S. Akbay and A. Chatterjee}, Booktitle = {Digest of 2nd IEEE Workshop on Test of Wireless Circuits and Systems, International Test Conference}, Month = {October}, Title = {Optimal Multisine Tests for {RF} Amplifiers}, Year = {2002}, Language = {English} } -------------------------------------------------------------------------------------------------------